1. Field of the Invention
The present invention relates to methods of isotropically etching silicon and devices formed thereby, particularly in the context of dense integration schemes employing FinFET devices.
2. Description of the Related Art
Semiconductor devices, such as RAM memory, are commonly used devices in computer applications. Typically, there is a strong desire to increase the density of these types of devices so as to improve device performance and reduce cost. For DRAM memory, there are two basic components, a charge storage cell and a gate for accessing the charge storage cell. As the need for increased density arises, there is a need for developing types of gates which are smaller in size to facilitate higher density of devices.
One type of gate device that is currently being used in a variety of applications, including memory applications, is a FinFET device. In general, a FinFET device is formed on a semiconductor substrate, such as a silicon substrate, on a silicon-on-insulator (SOI) substrate or other types of material. Typically, a fin is formed which is a vertically extending protrusion typically made of a semiconductor material, such as silicon. The fin has two vertical sidewalls over which a gate dielectric and a conductor can be positioned such that, when the conductor is charged, the resulting electric field creates channel regions in the fin that are controllable by the electric field on both sides of the fin. As a result of being able to control the channel regions from at least two sides of the fin, a conductive channel can be formed in the fin, which is smaller, thereby facilitating reduced device dimension with reduced leakage.
While FinFET devices provide advantages over traditional planar MOSFET devices, there is still a need to optimize the performance of FinFETs. In particular, reducing the threshold voltage to form the channel region and improving the scalability of the devices are important design considerations. Moreover, improving the refresh rate and improving the reliability of existing FinFET devices are also viewed as important objectives for obtaining even smaller FinFET devices to thereby allow for even greater device densities on semiconductor circuits such as DRAM devices and the like.
One way in which FinFET devices can be more effectively scaled is to improve the precision of processing steps used to create the devices. The inventors have recognized, for example, that greater control in silicon etching processes opens the door to greater flexibility in reliable device design and integration schemes for FinFET devices. Similarly, it will be appreciated that improved control in silicon etching would be beneficial for a variety of integrated circuit (IC) structures and processes, particularly where such etching defines lateral dimensions of IC features.